Course contents

Welcome to the e-Learning course focused on nano-CMOS cell design using Microwind, an educational tool for design, 2d and 3d view of the process, as well as analog simulation. The course illustrates the trends toward nano dimensions, the global technology roadmaps, with specific focus on voltage, power, manufacturability, MOS design, and inverter design. The Microwind tool and its lambda-based design is introduced. The MOS device is extensively analyzed, with focus on swtching performances, and options. The 20-nm technology implementation in Microwind as well as the 14-nm FinFET implementation are also illustrated.

  • Part 1 : General Trends (Download)
    • Meeting the Industrial 4.0 challenge : cyber-physics systems
    • The electronics market growth: from 1980 to 2020
    • The 1-tera € mobile phone business
    • Internet of Things and the Smart Cities
    • Towards automatic drive
  • Part 2 : Roadmap downto 5-nm (Download)
    • Future trends in nano-CMOS
    • Ultimate integration
    • MOS current drive - FinFET
    • Multi-patterning
    • Key parameters - 14, 10, 7 and 5nm
    • Post-MOS devices
  • Part 3 : Technology Trends (Download)
    • Towards 10-Giga Transistors
    • Data exchange between processor and memories
    • Supply voltage reduction
    • Tera-bit storage using 2.5D
    • Power and size reduction
    • Chip foundry costs
    • Roadmaps according to TSMC
    • Going 3D
  • Part 4: Introducing Microwind (Download)
    • What is Microwind
    • MOS models
    • Microwind features
    • Application notes
    • Lambda-based design
    • Design rules
  • Part 5 : The MOS device(Download)
    • nMOS design
    • 2D cross-section
    • MOS strain
    • Metal gate
    • Mos Models 1, 3 and BSIM4
    • nMOS as a switch
    • MOS Ion, Ioff, Ron
    • Adding properties for simulation
    • nMOS switching
    • pMOS design - polarization
    • pMOS strain
    • pMOS switching
    • Good and poor MOS designs
    • MOS options: low-leakage, high-voltage
    • Transmission gate - the perfect switch
  • Part 6 : The CMOS inverter (Download)
    • Inverter principles
    • Manual drawing
    • Delay vs. fanout
    • Delay vs. interconnect
    • Current consumption
    • 3-inverter ring oscillator
  • Part 7: Design for manufacturability (Download)
    • Dummy gate
    • Double patterning
    • Aligned fins in FinFETs
    • Interconnects
    • Student design manufacturability
  • Part 8 : 20-nm CMOS design (Download)
    • 20-nm Application note
    • MOS current drive trends
    • Scale down benefits - 20nm
    • Performance targets
    • 20-nm process overview
    • MOS options - Ion/Ioff trade-off
    • Dummy poly for manufacturability
    • Metal layers - double patterning
    • Ring oscillator study
    • Process, Temperature, supply variations
  • Part 9: FinFET implementation in Microwind (Download)
    • 14-nm
    • Introducing the FinFET
    • MOSFet vs. FinFET
    • 3D view of FinFETs
    • FinFET generator and design for manufacturability
    • FinFET current drive and performances
    • Interconnects, patterning
    • Inverter, Logic Gates, SRAM
    • 10-nm
    • 10-nm chips
    • Scaling trends, I/V perf.
    • PVT analysis of ring oscillators
    • SRAM in 10nm
    • 7-nm
    • I/V charact. of FinFET
    • Vt dependence vs. length
    • Performances vs Supply
    • Comparison 14-7nm

  • Reference Software

    The course is supported by the the software Microwind Etienne SICARD, INSA-Toulouse, Department of Electrical and Computer Engineering, France.

    The Teachers

    The teachers belong to GEI department of INSA Toulouse.


    Etienne SICARD

    Professor

    Sonia BEN DHIA

    Professor